The present invention relates to a multiplexer and, more particularly, to a multiplexer for inserting a frame synchronization code, a service code, or the like in a digital data signal train.
In a sending end in digital multiplex communications, a multiplexer having a function for multiplexing digital data signals and various code signals in time slots in response to a clock signal having a predetermined frequency plays an important role. FIG. 1 shows a conventional multiplexer. This multiplexer basically comprises a 1/M frequency divider 1, a 1/N frequency divider 2, and a selector 3.
FIG. 2 is a timing chart of signals generated in the multiplexer shown in FIG. 1. Referring to FIGS. 1 and 2, the frequency divider 1 receives a clock signal S10 for determining a length of one time slot and generates a signal S11 every M time slots. The signal S11 is input to the frequency divider 2 and to an input terminal S0 of the selector 3.
The frequency divider 2 generates N signals S22-1 to S22-N having different phases on the basis of the output signal S11 of the frequency divider 1. The signals S22-1 to S22-N are input to the input terminals S1 to SN of the selector 3, respectively. It should be noted that M usually represents 16 to 30 and N represents 4 to 8. For illustrative convenience, however, M=4 is given.
The selector 3 has (N+1) data input terminals D0 to DN, (N+1) control signal input terminals S0 to SN, and one data output terminal O. The data input terminal Di is paired with the corresponding control signal input terminal Si, where i is 0 to N. If the nth control signal input terminal Sn is set at logic "1" the signal input to the paired data input terminal Dn appears at the output terminal O.
Referring to FIG. 1, a digital data signal train S13-0 is input to the data input terminal D0 of the selector 3. The output signal S11 of the frequency divider 1 is input to the control signal input terminal S0. N insertion code signals S13-1 to S13-N are respectively input to the data input terminals D1 to DN of the selector 3. The output signals S22-1 to S22-N from the frequency divider 2 are respectively input to the control signal input terminals S1 to SN.
In the digital data signal string S13-0, each digital data signal using (M-1) time slots (three in this embodiment) and each gap G of one time slot alternately appear.
The signal S11 is set at logic "1" for three time slots in which digital data is present in the digital data signal train 13-0 and is set at logic "0" for one time slot in which digital data is not present therein.
The content of each of the N insertion code signals S13-1 to S13-N is kept unchanged for a time interval between the start and end output signals S22-1 and S22-N output from the frequency divider 2, as shown in FIG. 2. Therefore, the frequency of the insertion code signal is set to be 1/(N.times.M) of the digital data signal train S13-0.
The selector 3 outputs the digital data signal train S13-0 for a period in which the output signal S11 from the frequency divider 1 is kept at logic "1". However, the selector 3 outputs the insertion code signals S13-1 to S13-N in time slots respectively corresponding to the phases of the output signals S22-1 to S22-N from the frequency divider 2. As shown in FIG. 2, the insertion code signals (i05, i11, i12, i13, i14, i15, i21, . . . ) are properly inserted in the digital data signal train S13-0, thereby preparing a multiplexed signal S16.
An arrangement of the selector 3 used in FIG. 1 is shown in FIG. 3. The selector 3 includes (N+1) 2-input AND circuits 51-0 to 51-N and a plurality of multi-input OR gates 52, both of which constitute a multiple stage. A maximum operating frequency of the selector 3 is determined by the operating speeds of the respective logic circuits and propagation delay times between the respective stages. The selector 3 having the above arrangement is not suitable for high-speed digital signal processing, because it has to process signals of different speeds, i.e., the high-speed digital data signal train S13-0 and the low-speed insertion code signals whose frequency is 1/(N.times.M), e.g., a maximum of 1/240, of the digital data signal. In other words, the operating frequency of the multiplexer depends on the number of insertion code signals, and therefore, the high-speed multiplexing cannot be achieved. Also, when the total propagation delay time of the circuit is so long that a predetermined operating frequency cannot be obtained, the selector 3 must be opened at a predetermined position thereof, and a circuit element for controlling the operation timings must be inserted in the opened position.
This results in that the size of the selector 3 is increased in proportion to the number of insertion codes, and power consumption is undesirably increased.
Even if a relatively low frequency is set so as to allow use of MOS (metal oxide semiconductor) devices which consume less power and these devices are used, the propagation delay time of the circuit is further increased to greatly decrease the digital signal processing frequency.